skalp v0.2.0 Released

skalp v0.2.0 is out. The headline feature is a VHDL frontend — write standard VHDL-2008/2019 and feed it through the same synthesis, simulation, and verification pipeline as native skalp code.

Pre-built binaries are available for Linux, macOS, and Windows. Get it on GitHub.

VHDL Frontend

skalp now accepts VHDL as a first-class input language. The new skalp-vhdl crate provides a complete lexer, parser, and HIR lowering pass for a synthesizable subset of VHDL-2008/2019:

• Full synthesizable subset — entities, architectures, processes, signals, variables, generate statements, and component instantiation
• VHDL-2019 features — interfaces, mode views, generic type parameters, and generic package instantiation
• Hierarchical designs — multi-entity elaboration with end-to-end behavioral simulation
• VHDL-to-SystemVerilog transpilation — direct conversion through the HIR layer
• Testbench support — Rust async testbenches work with VHDL designs, same as skalp sources

Once parsed, VHDL designs enter the same MIR → LIR → SIR → backend pipeline as native skalp, so every optimization, analysis, and code generation pass applies equally.

Diagnostics

Error messages now use codespan-reporting for rustc-style diagnostics — source spans, colored labels, and fix suggestions rendered inline. This applies to both skalp and VHDL sources.

Tooling Improvements

• VS Code extension — available as a .vsix download on the GitHub release, with syntax highlighting, LSP integration, waveform viewer, schematic viewer, debugger, and testbench scaffolding for both skalp and VHDL
• VHDL LSP support — the language server handles VHDL files with semantic token highlighting and schematic support
• VHDL formatter — Wadler-Lindig pretty-printing for VHDL source
• skalp source formatter — skalp fmt rewritten with Wadler-Lindig pretty-printing
• HIR codegen — new code generation path from HIR to skalp, VHDL, and SystemVerilog with comment preservation, entity deduplication, and per-entity file output
• InputTiming — testbench control for waveform-aligned input drives

Reliability

• Stack overflow protection via stacker in the SIR and MIR passes
• Cross-process compilation serialization (flock) replacing in-process Mutex
• Compiler fingerprint in SIR cache key to prevent stale cache hits
• C++ and Metal shader compilation serialization to prevent OOM/SIGKILL

Bug Fixes

• Fixed async reset pattern causing double-increment in simulator
• Fixed dynamic array read/write in hierarchical elaboration
• Fixed multi-entity elaboration bugs causing simulation failures
• Fixed signal initial value propagation in MIR→SIR
• Fixed struct field access crash, CDC lifetime parameters, widening add operator
• Fixed parser infinite loop on real-world VHDL
• Fixed all VHDL parser gaps found across 6 stress-test projects
• Numerous codegen and always_ff generation fixes

See the full changelog for details.

Installation

Pre-built binaries

Download both binaries for your platform and add them to your PATH. The debug server (skalp-debug) is needed for VS Code debugging support.

VS Code extension

code --install-extension skalp-0.2.0.vsix

Download skalp-0.2.0.vsix from the GitHub release.

From source

cargo install --git https://github.com/girivs82/skalp --tag v0.2.0

Links

• GitHub release
• Project page
• Source code