skalp now accepts VHDL directly — including VHDL-2019 interfaces and views that no free tool supports. Your existing designs get CDC analysis, formal verification, gate-level simulation, and Rust async testbenches without rewriting a single line.
Technical whitepaper describing SKALP’s four-stage IR pipeline, compile-time clock domain safety through the type system, GPU-accelerated fault simulation on Apple Metal, and integrated ISO 26262 functional safety analysis.
skalp compiles hardware descriptions through four intermediate representations — HIR preserves intent, MIR models cycle-accurate RTL, LIR maps to technology primitives, and SIR optimizes for GPU simulation. How each IR serves a different purpose, what gets lowered at each stage, and why the synthesis and simulation paths diverge at LIR.