Hardware

Your first VHDL design compiled with skalp — an 8-bit counter that introduces entity/architecture, ports, rising_edge, skalp build, and basic simulation.

Your first skalp entity — an 8-bit counter that introduces the entity/impl split, port declarations, signal types, sequential logic with on(clk.rise), and combinational assignment.

Multiplexers, process(all), case/when, concurrent assignments, when…else, and with…select — all the ways VHDL expresses combinational logic, compiled with skalp.

Build a complete UART transmitter with FSM states, baud rate timing, and shift register serialization. Covers state encoding, counter-based timing, bit-level data shifting, and forward references for combinational signals.

Enumerated state types, FSM patterns with case statements, prescaler-based timing, and type casting — build a timer and an I2C-style controller, both compiled with skalp.

Generic parameters, array types, register banks, double-flop synchronizers, and edge-detect interrupts — build a GPIO controller with skalp.

Multi-entity designs, direct entity instantiation, port maps, internal signals, and named associations — connect a sender and receiver through a bus with skalp.

Make your designs fully configurable with generic defaults, explicit instantiation, compile-time width computation, const expressions, and test vs. production parameterization – all applied to the running UART project.

The skalp Testbench API — set, clock, expect, get_u64, export_waveform. Write async Rust tests for your VHDL designs without ModelSim, without license servers, just cargo test.

Group related signals into structs for cleaner interfaces, then compose entities hierarchically with let-binding to build the complete UART top-level module.