Chapter 7: skalp Integration

skalp pragmas for safety, CDC, and tracing. Formal verification of VHDL designs. Mixed skalp+VHDL projects. Get more from your VHDL with skalp-specific annotations.

March 4, 2026 · 19 min · Giri

Chapter 7: Enums and Pattern Matching

Enum types with explicit bit encoding, match expressions that return values, exhaustiveness checking that catches missing cases at compile time — refactor FSM states and build a UART command parser.

July 15, 2025 · 15 min · Giri

Chapter 8: VHDL-2019 Features

Interfaces, views, generic type parameters, and package instantiation — VHDL-2019 features that skalp supports and most free tools do not.

March 4, 2026 · 10 min · Giri

Chapter 8: Clock Domain Crossing

Clock domain lifetimes, CDC compile-time safety, dual-clock entities, 2-flop synchronizers, Gray code pointers, and async FIFOs — make the UART dual-clock with compile-time guarantees against metastability bugs.

July 15, 2025 · 22 min · Giri

Chapter 9: Real-World Project

Capstone: a parameterized SPI master with generics, generate statements, a five-state FSM, compile-time math, assertions, and a complete Rust test suite — all compiled and tested with skalp.

March 4, 2026 · 22 min · Giri

Chapter 9: Safety and Annotations

Add safety mechanisms and debug infrastructure to your designs with TMR voting, detection signals, retention hints, trace grouping, and simulation breakpoints – all zero-cost annotations that travel with your source code.

July 15, 2025 · 24 min · Giri

Chapter 10: Testing and Verification

Async Rust testbench API – Testbench::with_top_module(), tb.set(), tb.clock().await, tb.expect().await, tb.get_u64().await. Test organization, helper functions, multiple test cases, waveform generation, and a complete UART test suite.

July 15, 2025 · 17 min · Giri

skalp v0.2.0 Released

skalp v0.2.0 adds VHDL as a first-class input language — write VHDL, get the same synthesis pipeline, simulation, and verification that skalp programs get.

March 4, 2026 · 3 min · Giri

VHDL as a First-Class Frontend: Thirty Years of IP, Modern Tooling

skalp now accepts VHDL directly — including VHDL-2019 interfaces and views that no free tool supports. Your existing designs get CDC analysis, formal verification, gate-level simulation, and Rust async testbenches without rewriting a single line.

March 3, 2026 · 21 min · Giri

Why skalp Works the Way It Does: Design Choices and Their Justifications

skalp makes deliberate departures from VHDL and SystemVerilog conventions. Some feel unfamiliar; all are motivated by real problems in production hardware design. Fifteen design choices explained — what skalp does, the common pushback, what traditional HDLs do, and why skalp’s approach is right (with honest tradeoffs).

March 3, 2026 · 31 min · Giri