Chapter 1: Getting Started
Your first skalp entity — an 8-bit counter that introduces the entity/impl split, port declarations, signal types, sequential logic with on(clk.rise), and combinational assignment.
Your first skalp entity — an 8-bit counter that introduces the entity/impl split, port declarations, signal types, sequential logic with on(clk.rise), and combinational assignment.
Build a complete UART transmitter with FSM states, baud rate timing, and shift register serialization. Covers state encoding, counter-based timing, bit-level data shifting, and forward references for combinational signals.
Make your designs fully configurable with generic defaults, explicit instantiation, compile-time width computation, const expressions, and test vs. production parameterization – all applied to the running UART project.
Group related signals into structs for cleaner interfaces, then compose entities hierarchically with let-binding to build the complete UART top-level module.
Enum types with explicit bit encoding, match expressions that return values, exhaustiveness checking that catches missing cases at compile time — refactor FSM states and build a UART command parser.
Clock domain lifetimes, CDC compile-time safety, dual-clock entities, 2-flop synchronizers, Gray code pointers, and async FIFOs — make the UART dual-clock with compile-time guarantees against metastability bugs.
Add safety mechanisms and debug infrastructure to your designs with TMR voting, detection signals, retention hints, trace grouping, and simulation breakpoints – all zero-cost annotations that travel with your source code.
Async Rust testbench API – Testbench::with_top_module(), tb.set(), tb.clock().await, tb.expect().await, tb.get_u64().await. Test organization, helper functions, multiple test cases, waveform generation, and a complete UART test suite.
skalp v0.2.0 adds VHDL as a first-class input language — write VHDL, get the same synthesis pipeline, simulation, and verification that skalp programs get.
skalp now accepts VHDL directly — including VHDL-2019 interfaces and views that no free tool supports. Your existing designs get CDC analysis, formal verification, gate-level simulation, and Rust async testbenches without rewriting a single line.