skalp makes deliberate departures from VHDL and SystemVerilog conventions. Some feel unfamiliar; all are motivated by real problems in production hardware design. Fifteen design choices explained — what skalp does, the common pushback, what traditional HDLs do, and why skalp’s approach is right (with honest tradeoffs).
First release of skalp — an intent-driven hardware description language with compile-time clock domain safety, built-in synthesis, and native FPGA place & route.
Technical whitepaper describing SKALP’s four-stage IR pipeline, compile-time clock domain safety through the type system, GPU-accelerated fault simulation on Apple Metal, and integrated ISO 26262 functional safety analysis.
What does production skalp code actually look like? A tour of design patterns from two real projects and the broader language specification — covering state machines, type-safe control loops, stream pipelines, clock domain safety, inline constraints, and more. Each pattern compared with SystemVerilog.
A modern HDL written in Rust that preserves design intent from algorithm to gates, with compile-time clock domain safety and progressive refinement. ~221K lines across 24 crates.