skalp now accepts VHDL directly — including VHDL-2019 interfaces and views that no free tool supports. Your existing designs get CDC analysis, formal verification, gate-level simulation, and Rust async testbenches without rewriting a single line.
skalp makes deliberate departures from VHDL and SystemVerilog conventions. Some feel unfamiliar; all are motivated by real problems in production hardware design. Fifteen design choices explained — what skalp does, the common pushback, what traditional HDLs do, and why skalp’s approach is right (with honest tradeoffs).
First release of skalp — an intent-driven hardware description language with compile-time clock domain safety, built-in synthesis, and native FPGA place & route.
Technical whitepaper describing SKALP’s four-stage IR pipeline, compile-time clock domain safety through the type system, GPU-accelerated fault simulation on Apple Metal, and integrated ISO 26262 functional safety analysis.
skalp compiles hardware descriptions through four intermediate representations — HIR preserves intent, MIR models cycle-accurate RTL, LIR maps to technology primitives, and SIR optimizes for GPU simulation. How each IR serves a different purpose, what gets lowered at each stage, and why the synthesis and simulation paths diverge at LIR.
RTL simulation has been CPU-only for decades. skalp puts it on the GPU — starting with Metal on Apple Silicon, where unified memory means zero DMA. How SharedCodegen produces both Metal shaders and compiled C++ from the same core, what the simulation step looks like on a GPU, and why fault simulation at 10M faults/sec is embarrassingly parallel.
What does production skalp code actually look like? A tour of design patterns from two real projects and the broader language specification — covering state machines, type-safe control loops, stream pipelines, clock domain safety, inline constraints, and more. Each pattern compared with SystemVerilog.