Tutorial

The skalp Testbench API — set, clock, expect, get_u64, export_waveform. Write async Rust tests for your VHDL designs without ModelSim, without license servers, just cargo test.

Group related signals into structs for cleaner interfaces, then compose entities hierarchically with inst bindings to build the complete UART top-level module.

skalp pragmas for safety, CDC, and tracing. Formal verification of VHDL designs. Mixed skalp+VHDL projects. Get more from your VHDL with skalp-specific annotations.

Enum types with explicit bit encoding, match expressions that return values, exhaustiveness checking that catches missing cases at compile time — refactor FSM states and build a UART command parser.

Interfaces, views, generic type parameters, and package instantiation — VHDL-2019 features that skalp supports and most free tools do not.

Clock domain lifetimes, CDC compile-time safety, dual-clock entities, 2-flop synchronizers, Gray code pointers, and async FIFOs — make the UART dual-clock with compile-time guarantees against metastability bugs.

Capstone: a parameterized SPI master with generics, generate statements, a five-state FSM, compile-time math, assertions, and a complete Rust test suite — all compiled and tested with skalp.

Add safety mechanisms and debug infrastructure to your designs with TMR voting, detection signals, power and retention intent, trace grouping, and simulation breakpoints – all annotations that travel with your source code and are checked by the compiler.

Async Rust testbench API – Testbench::with_top_module(), tb.set(), tb.clock().await, tb.expect().await, tb.get_u64().await. Test organization, helper functions, multiple test cases, waveform generation, and a complete UART test suite.