Chapter 1: Getting Started
Your first VHDL design compiled with skalp — an 8-bit counter that introduces entity/architecture, ports, rising_edge, skalp build, and basic simulation.
Vhdl
Chapter 2: Combinational Logic
Multiplexers, process(all), case/when, concurrent assignments, when…else, and with…select — all the ways VHDL expresses combinational logic, compiled with skalp.
Chapter 3: Clocked Processes and State Machines
Enumerated state types, FSM patterns with case statements, prescaler-based timing, and type casting — build a timer and an I2C-style controller, both compiled with skalp.
Chapter 4: Generics, Records, and Arrays
Generic parameters, array types, register banks, double-flop synchronizers, and edge-detect interrupts — build a GPIO controller with skalp.
Chapter 5: Hierarchical Design
Multi-entity designs, direct entity instantiation, port maps, internal signals, and named associations — connect a sender and receiver through a bus with skalp.
Chapter 6: Testing VHDL with Rust
The skalp Testbench API — set, clock, expect, get_u64, export_waveform. Write async Rust tests for your VHDL designs without ModelSim, without license servers, just cargo test.
Chapter 7: skalp Integration
skalp pragmas for safety, CDC, and tracing. Formal verification of VHDL designs. Mixed skalp+VHDL projects. Get more from your VHDL with skalp-specific annotations.
Chapter 8: VHDL-2019 Features
Interfaces, views, generic type parameters, and package instantiation — VHDL-2019 features that skalp supports and most free tools do not.
Chapter 9: Real-World Project
Capstone: a parameterized SPI master with generics, generate statements, a five-state FSM, compile-time math, assertions, and a complete Rust test suite — all compiled and tested with skalp.
skalp v0.2.0 Released
skalp v0.2.0 adds VHDL as a first-class input language — write VHDL, get the same synthesis pipeline, simulation, and verification that skalp programs get.