Choose Your Track

skalp compiles both its own language and VHDL. Pick the tutorial that matches your background:

skalp Language Tutorial

Build a complete UART peripheral from scratch.

10 chapters that take you from your first entity to clock domain crossings, safety annotations, and Rust-based testbenches. Best if you want to learn the skalp language itself.

  1. Getting Started — Entities, signals, on(clk.rise)
  2. State Machines — UART transmitter with FSM and baud timing
  3. UART Receiver — Mid-bit sampling and edge detection
  4. Arrays and Generics — Parameterized FIFO buffering
  5. Parameterization — Const generics and configurable designs
  6. Structs and Composition — Hierarchical design with struct ports
  7. Enums and Matching — Type-safe FSMs with exhaustive matching
  8. Clock Domain Crossing — CDC safety with clock lifetimes
  9. Safety and Annotations — TMR, trace, breakpoints
  10. Testing — Async Rust testbenches with full coverage

VHDL with skalp Tutorial

Use your existing VHDL designs with skalp’s compiler, simulator, and Rust test framework.

9 chapters that walk through progressively complex VHDL designs — counters, FSMs, generics, hierarchical systems — compiled and tested with skalp. Best if you already know VHDL and want to use skalp as your build and verification tool.

  1. Getting Started — Compile and simulate counter.vhd
  2. Combinational Logic — Multiplexers, process(all), case/when
  3. Clocked Processes and FSMs — Timers, I2C controller, enumerations
  4. Generics, Records, and Arrays — GPIO controller, edge detection
  5. Hierarchical Design — Multi-entity systems, port maps
  6. Testing VHDL with Rust — Testbench API, waveforms, coverage
  7. skalp Integration — Pragmas, formal verification, mixed designs
  8. VHDL-2019 Features — Interfaces, views, generic types
  9. Real-World Project — SPI master capstone with full test suite